In the past, metal interconnects were typically formed in semiconductor devices by depositing a layer of aluminum on a substrate, patterning the aluminum to form the desired interconnects, and then filling the spaces between the interconnects with a suitable dielectric material such as silicon oxide. More recently, it has become desirable to substitute copper for aluminum in many interconnect applications, due to the lower resistivity and lower susceptibility to electromigration (EM) failure of copper as compared to aluminum. Since copper interconnects, unlike their aluminum counterparts, cannot be easily formed by depositing and patterning a layer of the metal on a substrate, this substitution has necessitated the development of a different fabrication process (referred to in the art as a damascene or inlaid process) for the formation of copper interconnects.
One known embodiment of the damascene process is illustrated in FIGS. 1-5. As seen in FIG. 1, at the beginning of that process, an inter-level dielectric (ILD) 103 is blanket deposited over a substrate 101, the latter of which will often be an integrated circuit structure. A cap layer 105, which may comprise a material such as tetraethylorthosilicate glass (TEOS), is then formed over the ILD 103.
With reference to FIG. 2, one or more trenches 107 having a geometry conforming to the desired pattern of copper metal interconnects are then formed in the ILD 103. A barrier metal 109 is deposited over the ILD 103 (and over the surfaces of the trenches 107 defined therein) to facilitate adhesion between the ILD 103 and the subsequently deposited copper layer 111 (see FIG. 3), and to prevent migration of the copper into the ILD 103.
As seen in FIG. 3, a layer of copper metal 111 is then blanket deposited over the structure. This copper layer 111 fills the trenches 107 (see FIG. 2) and also forms a layer that extends over the cap layer 105.
As seen in FIG. 4, the excess copper, the cap layer 105 and a portion of the adhesion promoting layer 109 are removed from the surface of the ILD 103 by a chemical mechanical polishing (CMP) process, thus leaving the desired pattern of copper metal interconnects 111 in the trenches formed in the ILD 103. Then, the exposed surfaces of the copper interconnects 111 are treated with a reducing plasma such as NH3/N2 to remove copper oxide from the surfaces thereof, and to improve the resistance of the copper interconnects 111 to electromigration. Treatment with the reducing plasma also serves to facilitate adhesion between the copper interconnects 111 and the subsequently deposited barrier film 115, which is depicted in FIG. 5.
The foregoing process for forming copper metal interconnects may also be combined with a process for forming copper-filled vias by using a stack of two dielectric layers, with via openings formed in the lower dielectric layer and trench openings formed in the upper dielectric layer. Both the vias and the trenches are then backfilled with copper during a single copper deposition step. In this process, commonly referred to in the art as a dual damascene or dual-inlaid process, excess copper is again removed from the surface of the upper layer of dielectric material by CMP, leaving behind a pattern of copper metal interconnects that are vertically connected by copper-filled vias to the underlying integrated circuit structure.
In both the damascene and dual damascene processes as they are typically implemented in the formation of advanced integrated circuit devices, an ILD is typically used to electrically separate the closely spaced metal interconnect lines that are arranged on several levels in the device. In the past, the material of choice for this ILD was silicon oxide, which has a k-value or dielectric constant of 4.2. However, as circuit densities have increased, it has become desirable, in order to minimize capacitive coupling and cross-talk between adjacent metal lines, to use ILD materials in these applications that have dielectric constants or k-values that are even lower, and that are ideally as close to 1 as possible. This has led to the replacement of silicon oxide in ILDs with other, lower dielectric constant materials, such as carbon-doped silicon oxides. Depending on their dielectric constants, such materials are referred to as low-k dielectrics (for materials having k values of less than 4.1) or ultra low-k dielectrics (for materials having k values of less than 2.7).
One result of damascene processing is that the ILD is exposed to a greater number of processing steps. At the same time, the low-k and ultra low-k dielectrics utilized in the ILD are more prone to processing related damage than silicon oxide. For example, in the process depicted in FIGS. 1-5, the exposure of the ILD to the NH3-based reducing plasma, which is required to impart a good, low oxide metal surface to the copper layer 111, can damage the ILD 103 and increase the dielectric constant thereof. Specifically, if the ILD is a carbon-doped silicon oxide film, exposure of that film to reducing plasmas can result in carbon depletion and densification of the film, which can lead to an increase in the k-value of the integrated ILD film. Perhaps for this reason, the low-k ILDs utilized in damascene processes typically exhibit dielectric constants which are substantially higher than the values that are theoretically achievable with these materials. This increase in dielectric constant adversely affects device performance, and also stands as a significant impediment to the scalability of damascene processes.
Several variations in the damascene and dual damascene processes described above are also known to the art, and some of these variations do not utilize a reducing plasma to remove oxides from the copper interconnects. One such variation involves the use of a metallic copper diffusion barrier that is selectively plated onto the copper interconnects after the CMP step in either standard damascene or dual damascene processing. This metallic barrier can be plated by electroless or electroplated processes. Typically, electroless plated films, such as CoWB or CoWP, are utilized for this purpose. The use of metallic barrier films offer improved EM performance. Moreover, the use of such barrier films permits the elimination of dielectric copper barrier materials. Since these barrier films are typically higher-k films than the ILD, their removal reduces the integrated k-value of the overall interconnect film stack.
Although the ILD is not exposed to a reducing plasma for the treatment of the copper interconnects in such a process, the ILD is exposed to an oxidizing plasma during the deposition of dielectric layers for subsequent levels of interconnect. These dielectric layers may be adhesion promoting layers or the subsequent ILD layer. Unfortunately, it has been found that oxidizing plasmas, like reducing plasmas, also damage low-k dielectric films, and that integrated ILD layers subjected to this process suffer a similar increase in dielectric constant.
There is thus a need in the art for a process which overcomes these infirmities. In particular, there is a need in the art for a method for making semiconductor devices by a damascene or dual damascene process in which the dielectric constant of the ILD in the resulting device is closer to theoretically achievable values. There is further a need in the art for such a method in which the films are less susceptible to damage from subsequent processing steps and conditions, including exposure to oxidizing or reducing plasmas. These and other needs may be met by the methodologies and devices described herein.